< table border = "1" > < tr > < th > Specification th > < th > Details th > tr > < tr > < td > Processor Architecture td > < td > Zen 5 td > tr > < tr > < td > # of CPU Cores td > < td > 16 td > tr > < tr > < td > Multithreading (SMT) td > < td > Yes td > tr > < tr > < td > # of Threads td > < td > 32 td > tr > < tr > < td > Max. Boost Clock td > < td > Up to 5.7 GHz td > tr > < tr > < td > Base Clock td > < td > 4.3 GHz td > tr > < tr > < td > L1 Cache td > < td > 1280 KB td > tr > < tr > < td > L2 Cache td > < td > 16 MB td > tr > < tr > < td > L3 Cache td > < td > 128 MB td > tr > < tr > < td > Default TDP td > < td > 170W td > tr > < tr > < td > Processor Technology for CPU Cores td > < td > TSMC 4nm FinFET td > tr > table >